Semiconductor memory devices are well-known in the prior art. Memory cells are generally configured into arrays of rows and columns as shown in FIG. 1. As shown in FIG. 1, a column of memory cells comprises a number of cells which share a pair of common bit lines, such as column 3 which shares bit lines B.sub.3 and B.sub.3 . Each pair of bit lines accesses the true and complement data stored in a selected one of the memory cells within a column. Similarly, a row of memory cells comprises cells sharing a common word line. Each word line selects a row of memory cells to be accessed by the bit lines.
Semiconductor manufacturing techniques for fabricating memory devices have improved tremendously over the last two decades resulting in increased yields. However, a higher level of integration, i.e. a larger number of elements of smaller sizes, is also achieved over the same period. Yields have approached but not achieved the theoretically possible target of 100%. At the same time, design techniques are increasingly being used to compensate for manufacturing flaws and to further improve yields.
In semiconductor memories, some of the design techniques involve providing redundant memory cells on the devices and redirecting the addressing circuitry to configure the redundant cells in place of the defective memory cells. Consequently, many defective memory devices can be transformed into fully operable memory devices. Various ways of addressing these redundant cells in place of defective cells have been implemented.
A conventional way of implementing memory cell redundancy is to provide "row redundancy" with one or more redundant rows of memory cells. In one such method, each redundant row is equipped with programmable links, such as fuses, so that a redundant row can be programmed into the address location of a defective row. These fuses have to be individually programmed for each replacement row location and a complex mapping algorithm is necessary to locate the appropriate fuses to be blown.
An alternative solution which avoids the above complex mapping problem uses "column redundancy". Squads, each comprised of a small fixed number of columns of memory cells, generally about four columns to a squad, are organized into groups. The number of squads in each group is limited to four to six (with four to six corresponding fuses in series). Each group of squads is associated with a redundant squad. Such a redundant squad contains the same number of columns as a regular squad and can be shifted in to replace a defective squad (with one or more defective columns) within the group. Hence, one-sixth to one-quarter of the total number of memory cells are redundant. As a result, this redundant squad column solution does not allow for the minimization of the total number of redundant cells required to fix the relatively small number of defective memory cells in a typical semiconductor device. A "squad column redundancy" circuit is shown in FIG. 2. Note the resistive ladder of fuses 20, 30, . . . coupled between a logic high voltage source (Vcc) and a fuse ground circuit.
A second "row redundancy" method, called "adjacent row redundancy", appears to solve both the complex mapping problem and the redundant cell minimization problem. To use this method, a fairly large number of rows of memory cells are organized into groups. In a typical memory device, there may be 128 to 256 rows in each group. Here, a redundant row is provided for each group of rows. A prior art circuit for accomplishing row shift redundancy comprises a resistive fuse ladder, one end of which is tied to power, the other end of which is tied to ground. Any fuse in the ladder could be severed at the point where the shift would begin within a group of rows.
A major difficulty associated with the "adjacent row redundancy" method is the long string of fuses required, since 128 or 256 rows would require 128 to 256 fuses in series. Typically, each fuse adds about 250 Ohms to the total series resistance of the resistor string. This results in possible resistive degradation of the programmed level and/or capacitive coupling into the high impedance fuse line that could introduce circuit malfunction. In practice, the length of the resistive fuse ladder is limited by the cumulative series resistance and the capacitance of the series of fuses 20, 30, . . . 70, 80, 90 as represented in FIG. 3.
FIG. 4 shows an adjacent row redundancy circuit having a long resistive ladder of programmable fuses. When there is a defective row, one of the fuses in the resistive ladder such as 20, 30, 40, 50, . . . or 90 is blown to provide the replacement redundant row. In a typical device, a portion of the resistive fuse ladder comprises a number of fuses equal in number to at least half the number of rows, i.e. at least 64 or 128 fuses in series. Although one end of this portion of the resistive fuse ladder is connected to either node 59 at Vcc or to node 60 at fuse ground, the other end of this portion of the fuse ladder is now floating. The result is a high impedance line highly susceptible to resistive and/or capacitive coupling.